View AD8366_4297691.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Preliminary Technical Data
FEATURES
Matched Pair of Differential Digitally-Controlled VGAs Gain Range: 4.5 dB to 20.5 dB Step 0.25 dB Operating frequency DC to 500MHz 800MHz 3-dB bandwidth NF 10.5 dB @ max. gain, 18dB @ min. gain at 10MHz OIP3 36dBVrms at 10MHz HD2, HD3 > 88dBc for 2Vpp output at 10MHz at max gain Differential Input and Output Adjustable output common-mode Optional DC output offset correction Serial/Parallel Port Programmable Power-down Feature Single 5V Supply Operation
DC to 500 MHz, Dual Digital Gain Trim Amplifier AD8366
FUNCTIONAL BLOCK DIAGRAM
Ch. A Data Enable Ch. B Data Enable
AD8366
IAN
DC OFFSET CANCELLATION
OAN
IAP VCMA
OAP
VCMB IBP
DC OFFSET CANCELLATION
OBP
APPLICATIONS
Baseband I/Q receivers Diversity receivers ADC drivers W-CDMA/CDMA/CDMA2000/GSM Point-to-(Multi)Point Radio CATV Wireless local loop WiMax
IBN
OBN
CHANNEL GAIN CONTROL
B0 B1 B2 B3 B4 B5
Serial / Parallel
Figure 1. Functional Block Diagram
GENERAL DESCRIPTION
The AD8366 is a matched pair of fully differential low-noise and low-distortion digitally programmable variable gain amplifiers. The gain of each amplifier can be programmed separately or simultaneously over a range of 5 dB to 21 dB in steps of 0.25 dB. The amplifier offers flat frequency performance and group delay from DC out to 150 MHz, independent of gain code. The AD8366 offers excellent spurious-free dynamic range, suitable for driving 12-bit ADCs. The NF at max gain is 10.5 dB at 10 MHz and increases 2dB for every 4dB decrease in gain. Over the entire gain range, the HD3 and HD2 are >88dBc for 2 V p-p at the output at 10 MHz into 500 . The 2-tone intermodulation distortion of -90dBc into 200 translates to an OIP3 of 43 dBm. The differential input impedance is 200 to provide a well-defined termination. The differential output is voltage-mode with a low impedance of 30 .
Rev. PrC
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
The output common-mode defaults to Vps/2 but can be programmed via pins VCMA and VCMB over a range of voltages. The built-in DC-offset compensation loop can be disabled if DC-coupled operation is desired. The high-pass corner is defined by external capacitors on pins OFSA and OFSB. The input common mode also defaults to Vps/2 but can be driven from 1.2V to 3.4V. The digital interface allows for parallel or serial gain programming. The AD8366 operates off a 4.5V to 5.5V supply and consumes a supply current of 175mA. When disabled, it consumes ~ 4mA. The AD8366 is fabricated using Analog Devices' advanced Silicon-Germanium bipolar process and is available in a 32-lead exposed paddle LFCSP package. Performance is specified over a -40oC to +85oC temperature range.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
AD8366 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5
Preliminary Technical Data
ESD Caution...................................................................................5 Pin Configuration and Function Descriptions..............................6 Typical Performance Characteristics ..............................................7 APPLICATIONS SCHEMATIC......................................................8 Parallel and SERIAL Interface timing.............................................9 Outline Dimensions ....................................................................... 13
REVISION HISTORY
10/07--Revision PrA: Initial Version 02/08--Revision PrB: Updated Performance Specifications 06/08--Revision PrC: Evaluation Board Section
Rev. PrC | Page 2 of 13
Preliminary Technical Data SPECIFICATIONS
VS. = 5 V, TA = 25C, Zs = 200 , ZL = 200 , f = 10 MHz, unless otherwise noted Table 1.
Parameter DYNAMIC PERFORMANCE Bandwidth Slew Rate INPUT STAGE Maximum Input Swing Differential Input Impedance Input Common Mode Range GAIN Voltage Gain Range Gain Step Size 0.1dB Gain Flatness Mismatch Group Delay Flatness Mismatch Gain Step Response Common-mode Rejection Ratio OUTPUT STAGE Maximum Output Swing Differential Output Impedance Output DC offset Output Common Mode Range Common-Mode Setpoint Input Impedance NOISE/DISTORTION 10 MHz Noise Figure 2nd Harmonic 3rd Harmonic OIP3 Output 1 dB Compression Point 50 MHz Noise Figure 2nd Harmonic 3rd Harmonic Conditions 3dB; all gain codes 1dB; all gain codes Max. Gain Min. Gain IPPA, IPMA, IPPB, IPMB At minimum gain Av=4.5dB 1Vp-p Input Input pins left floating TBD Vps/2 4.5 All gain codes Max. Gain Channels A and B at same gain code All gain codes, 20% frac. bandwidth, fc<100MHz Channels A and B at same gain code Max. gain to Min. gain Min. gain to Max gain OPPA, OPMA, OPPB, OPMB, VCMA, VCMB At maximum gain, Av=20.5dB Inputs Shorted, offset loop disabled 1Vp-p output VCMA and VCMB left floating -15 1.2 0.25 150 +/0.05dB <0.5 2 TBD TBD TBD 6 30 TBD Vps/2 4 Min Typ 1000 250 TBD TBD 3.2 200
AD8366
Max
Unit MHz MHz V/ns V/ns Vp-p V
TBD
20.5
dB dB MHz dB ns ps ns ns dB Vp-p mV V V k
-4 3.4
Max Gain Min Gain 2 Vp-p output, Max Gain, ZL=500 2 Vp-p output, Min Gain, ZL=500 2 Vp-p output, Max Gain, ZL=500 2 Vp-p output, Min Gain, ZL=500 2 V p-p composite, Max. Gain, ZL=200 2 V p-p composite, Min. Gain, ZL= 200 Max. gain, ZL=500 Min. Gain, ZL=500 Max Gain Min Gain 2 Vp-p output , Max Gain Min Gain 2 V p-p output, Max Gain Min Gain
Rev. PrC | Page 3 of 13
10.5 18 88 88 92 85 36 35 7 6.9 11.2 18.5 TBD TBD TBD TBD
dB dB dBc dBc dBc dBc dBVrms dBVrms dBVrms dBVrms dB dB dBc dBc dBc dBc
AD8366
OIP3 Output 1 dB Compression Point 100 MHz Noise Figure 2nd Harmonic 3rd Harmonic OIP3 Output 1 dB Compression Point DIGITAL LOGIC VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance SPI INTERFACE TIMING fSCLK t1 t2 t3 t4 t5 t6 PARALLEL PORT TIMING t7 t8 t9 t10 POWER AND ENABLE Supply Voltage Range Total Supply Current Disable Current Disable Threshold Enable Response Time Disable Response Time 2 V p-p composite, Max. Gain, ZL=500 2 V p-p composite, Min. Gain, ZL=500 Max. gain, ZL=500 Min. Gain, ZL=500 Max Gain Min Gain 2 Vp-p output , Max Gain Min Gain 2 Vp-p output, Max Gain Min Gain 2Vp-p composite, Max. Gain @ 500 Load impedance Min. Gain Max. gain Min. Gain SENB, DENA, DENB, BIT0, BIT1, BIT2, BIT3, BIT4, BIT5
Preliminary Technical Data
34.2 30.7 6.7 7.2 11.84 18.8 TBD TBD TBD TBD 29.5 21 4 6 TBD TBD TBD TBD SENB = HIGH TBD CS rising edge to first SCLK rising edge SCLK high pulse width SCLK low pulse width SDAT setup time SDAT hold time SCLK falling edge to CS low SENB = LOW DENA/B high pulse width DENA/B low pulse width BIT[0-5] setup time BIT[0-5] hold time VPSI, VPSO, ICOM, OCOM, ENBL ENBL = 5V ENBL = 0V Delay following high-to-low transition until device meets full specifications Delay following low-to-high transition until device produces full attenuation TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 4.5 180 3.2 TBD TBD TBD 5.5 MHz ns ns ns ns ns ns ns ns ns ns V mA mA V ns ns dBVrms dBVrms dBVrms dBVrms dB dB dBc dBc dBc dBc dBVrms dBVrms dBVrms dBVrms V V A pF
Rev. PrC | Page 4 of 13
Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltages VPSI, VPSO ENBL, SENB, DENA, DENB, BIT0, BIT1, BIT2, BIT3, BIT4, BIT5 IPPA, IPMA, IPPB, IPMB OPPA, OPMA, OPPB, OPMB OFSA, OFSB DECA, DECB, VCMA, VCMB, CCMA, CCMB Internal Power Dissipation JA (With Pad Soldered to Board) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering 60 sec) Rating 5.5 V TBD V TBD V TBD V TBD V TBD V TBD mW TBDC/W 125C -40C to +85C -65C to +150C 300C
AD8366
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. PrC | Page 5 of 13
AD8366 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DECA OFSA CCMA VCMA VPSOA OPPA OPMA SENB
Preliminary Technical Data
32 31 30 29 28 27 26 25
VPSIA IPPA IPMA ENBL ICOM IPMB IPPB VPSIB
1 2 3 4 5 6 7 8
AD8366
TOP VIEW
24 23 22 21 20 19 18 17
BIT0/CS BIT1/SDAT BIT2/SCLK BIT3 OCOM BIT4 BIT5 DENA
Table 3. Pin Function Descriptions
Pin No. 1, 8, 13, 28 2, 3, 6, 7 4 5, 20 9, 32 10, 31 11, 30 12, 29 14, 15, 26, 27 16, 17 18, 19, 21, 22, 23, 24 Mnemonic VPSIA, VPSIB, VPSOA, VPSOB IPPA, IPMA, IPPB, IPMB ENBL ICOM, OCOM DECA, DECB OFSA, OFSB CCMA, CCMB VCMB, VCMA OPPB, OPMB, OPMA, OPPA DENB, DENA BIT5, BIT4, BIT3, BIT2, BIT1, BIT0 SENB Description Input and Output Stage Positive Supply Voltage. 4.5 V - 5.5 V. Differential Inputs Chip Enable. Pull high to enable. Input and Output Stage Common. Connect via lowest possible impedance to external circuit common Vpos/2 Reference Output Decoupling. Connect decoupling capacitor to circuit common. Output Offset Correction Loop Compensation. Connect capacitor to circuit common. Tie to common to disable. Output Common-mode Centering Loop Compensation. Connect capacitor to circuit common Output Common-mode Setpoint. Defaults to Vpos/2 if left open Differential Outputs Data enable . Pull high to address each or both channels for parallel load. Not used in serial mode. Parallel data path for SENB pulled low. For SENB pulled high, BIT0 becomes a chip-select (CS), BIT1 becomes serial data input, SDAT, and BIT2 becomes serial clock, SCLK. BIT3-BIT5 are not used in the serial mode Serial interface enable. Pull high for serial; pull low for parallel.
25
DECB OFSB CCMB VCMB VPSOB OPPB OPMB DENB
Figure 2. Pin Configuration
Rev. PrC | Page 6 of 13
9 10 11 12 13 14 15 16
Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS
1 0.75 0.5 0.25 0 -0.25 -0.5 -0.75 -1 0 4 8 12 16 20 24 28 32 36 40 44 48
10MHz
AD8366
50MHz
Error (dB)
100MHz
52
56
60
64
Gaincodes
Figure 3. Gain vs. Frequency for Multiple Gain Codes
Figure 6. Gain Error vs. Ideal Gain Codes at 10MHz, 50MHz and 100MHz
1
0.5 0.4 0.3 0.2
IQ P ha se M is m a tc h (d B )
0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3
Gain M ism atch (dB)
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12.5 13.5 Ideal Gain (dB) 14.5 15.5 16.5 17.5 18.5 19.5 20.5
-0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Ideal Gain (dB)
Figure 4. IQ Gain Mismatch at 10 MHz vs. Ideal Gain
90 20
10.00
Figure 7. IQ Phase Mismatch at 10 MHz vs. Ideal Gain
22.00 21.00 20.00
80
OIP2
18 16
8.00
70
6.00 19.00
NF
14
4.00
O IP 3 (d B m ) , O IP 2 (d B m )
12 50
O u tp u t o f D U T (d B V rm s )
60
18.00 2.00 17.00 16.00 15.00 14.00 -4.00 13.00
N o is e F ig u re (d B )
OIP3
40
10 8
0.00
-2.00
30 6 20 4 2 0 4 6 8 10 12 14 16 18 20 22
-6.00 12.00
10
-8.00
11.00 10.00 -19.00 -17.00 -15.00 -13.00 -11.00 -9.00 -7.00 -5.00 -3.00 -1.00
0
-10.00 -21.00
Gain (dB)
Input (dBVRMS)
Figure 5.O IP2,OIP3 and NF vs. Gain at 10 MHz
Figure 8. Gain & Output Swing vs. Input Power at Max Gain Setting at 10MHz
Rev. PrC | Page 7 of 13
G a in (d B )
AD8366 APPLICATIONS SCHEMATIC
Preliminary Technical Data
VPOS
0
0.01F
VPOS 10k
0.1F
0.01F
VPOS
0
COFS 0.01F
1000pF
Vin
PARALLEL / SERIAL CONTROL INTERFACE (PCI)
DECA
CCMA OFSA
VPSOA VCMA
OPMA SENB BIT0
VPSIA IPPA IPMA
OPPA
BIT1 BIT2
VPOS
ENBL ICOM IPMB IPPB VPSIB
AD8366
BIT3 OCOM BIT4 BIT5
DENA VCMB OPPB DENB OFSB CCMB OPMB DECB VPSOB
VPOS
0
0.01F
Vin
COFS 1000pF
10k
0.01F
0.01F
0
0.1F
VPOS
Figure 9 Applications Schematic with Basic Connections
Rev. PrC | Page 8 of 13
VPSI_A
VPSI_A VPSI_B
R79
ENBL
R22 R10 C22 C28
VCMA
R28 R24
VCMB
S1 C30 C2 R67 C11 R30 R70
C9 C24
VPSO_B
S11
EVALUATION BOARD
VPOS VPSO_A
R3 C15 R71 R35 R6 C16 R65 R29 R69
R40 S4
VPSI_A
VCM A VPSO_A
VPSI_A
R5
C1
C13
R4 T3 R39 R34
VPSI_A
VPSI_B
Preliminary Technical Data
C14
C26
R18
C4
VPSI_A
DECA VPSOA VCMA OPPA SENB BIT0 OPMA CCMA OFSA
R45
R54
R13 R50
VPSIA IPPA IPMA BIT2 BIT1
BIT2
C18
T1
R61 C33 R41
S9
VPSI_A
C20
Figure 10. Evaluation Board Schematic
Rev. PrC | Page 9 of 13
R12 R48
ENBL
ENBL ICOM IPMB IPPB VPSIB
R14
S2 R42
VPSI_A
VPSI_A S6
R17
R44
AD8366
BIT3 OCOM
R21 R46
R63
R43
BIT4 BIT5
VPSI_A S8 R64 S10 VPSI_A R53 C29 R57 VPSI_A S7 S5
R16 R62
VPSI_B
C21
T1
C5
DENA VCMB OPPB DENB OFSB CCMB OPMB DECB VPSOB
R19 R58
R15
R20
R47
C17
VCMB VPSO_B
C31
R80
C10
R74 R33
S12
R37
VPSI_A
R26 S3
U1
R73 C12 R68 C3 R72
C25
R32
C23
T4 R31 R36 R38
C27
BIT2
AD8366
AD8366
Table 4. Evaluation Board Configuration Options
Components C1, C13 to C16, R3 to R6
Preliminary Technical Data
Function Power Supply Decoupling. Nominal supply decoupling consists a 0.1F capacitor to ground followed by 0.01 F capacitors to ground positioned as close to the device as possible. Input Interface. The default configuration of the Eval board is for single ended operation. T1 and T2 are 4:1 impedance ratio baluns to transform a 50 single-ended input into a 200 -balanced differential signal. R12 to R14 and R15, R16, and R19 are populated for appropriate balun interface. R44 to R48 and R50, R54, R58, R62, andR63 are provided for generic placement of matching components. C5 to C20 are balun decoupling capacitors. R17, R18, R20, R21 can be populated with 0 and the balun interfacing resistors can be removed to bypass T1 and T2 for differential interfacing. Output Interface. The default configuration of the Eval board is for single ended operation. T3 and T4 are 4:1 impedance ratio baluns to transform a 50 single-ended output into a 200 -balanced differential load. R29 to R31, R33, R38, R39 are populated for appropriate balun interface. R65, R67 to R74, and R80 are provided for generic placement of matching components. C24, C25 are balun decoupling capacitors. R34 to R37 can be populated with 0 and the balun interfacing resistors can be removed to bypass T3 and T4 for differential interfacing. Enable Interface. -Device Enable. The AD8366 is enabled by applying a logic high voltage to the ENBL pin. The device is enabled when the switch S1 is set in the down position (HIGH), connecting the ENBL pin to VPOS. -Data Enable. DENA and DENB are used to enable the data path for Channel A and Channel B respectively. Channel A is enabled when the switch S5 is set in the down position (HIGH), connecting the DENA pin to VPOS. Likewise, Channel B is enabled when the switch S7 is set in the down position (HIGH), connecting the DENB pin to VPOS. Both channels are disabled by setting the switches to the up position, connecting the DENA and DENB pins to GND. Serial/Parallel Interface Control. SENB is used to set the data control either in parallel or serial mode. Parallel Interface is enabled when the switch S4 is up position (LOW). Serial interface enabled when S4 is in the down position (HIGH). For SENB pulled LOW, BIT0 (switch S9) sets 0.25dB Gain BIT1 (switch S2) sets 0.5dB Gain BIT2 (switch S3) sets 1dB Gain BIT3 (switch S6)sets 2dB Gain BIT4 (switch S8)sets 4dB Gain BIT5 (switch S10) sets 8dB Gain For SENB pulled HIGH, BIT0 becomes a chip-select (CS), BIT1 becomes serial data input, SDAT, and BIT2 becomes serial clock, SCLK. BIT3-BIT5 are not used in the serial mode. DC Offset Correction Loop Compensation. The DC offset correction loop is enabled (HIGH) with switch S11 and S12 for channel A and channel B respectively. When enabled, the capacitor is connected to circuit common. When disabled (LOW), the OFSA/OFSB pins are tied to common.
T1, T2, C5,C18,C20,C21, R12 to R21, R44 to R48, R50, R54, R58, R62, R63
Default Conditions C1 = 0.1F (size 0603) C13 to C16 = 0.01 F (size 0402) R3 to R6 = 0 (size 0603) T1, T2 = ADT4-6T+ (Mini-Circuits) C5,C20 = 0.1 F (size 0402) C18,C21 = Do not install R12 to R16, R19, R44 to R47= 0 (size 0402) R17, R18, R20, R21,R48, R50, R54, R58, R62, andR63 = open (size 0402)
T3, T4, C24 to C27, R29 to R31,R33 to R39,R65,R67 to R74, R80
T3, T4 = ADT4-6T+ (Mini-Circuits) C24,C25 = 0.1 F (size 0402) C26,C27 = Do not install R29 to R31, R33, R38, R39, R65, R67, R68, R80 = 0 (size 0402) R34 to R37, R69 to R74= open (size 0402)
S1, S5, S7, R53, R57, R79, C29, C30, C31
S1,S5,S7 = installed R53, R57= 5.1k (size 0603) R79 = 10k (size 0402) C30=0.01uF (size 0402) C29, C31=1500pF (size 0402)
S2,S3,S4,S6,S8,S9, S10 R26, R32, R40-R43, R61,R64 C23, C33 U1
S2,S3,S4, S6, S8, S9, 10 = installed R26=698 k (size 0603) R32, R40-R43, R61,R64 = 5.1k (size 0603) C23, C33 = 1500pF (size 0603) U1= SN74LVC2G14, Clock Chip
S11, S12, C9, C10
S11, S12 = installed C9, C10=8200pF (size 0402)
Rev. PrC | Page 10 of 13
Preliminary Technical Data
R10, R22, R24, R28, C22, C28 Output Common-mode Setpoint. The output common mode on channels A and B can be set externally when applied to the VCMA and VCMB. The resistive change thorough the potentiometer sets a variable VCMA voltage. If left open, the output common mode defaults to Vpos/2. Vpos/2 Reference Output Decoupling Capacitor to circuit common. Output Common-mode Centering Loop Compensation. Connect capacitor to circuit common
AD8366
R10, R24= 10 k Potentiometers R22, R28= 0
C2, C3, C11, C12 C4, C17
C2, C3= 0.1F (size 0402) C11, C12= 0.01F (size 0402) C4, C17= 1 nF (size 0402)
Rev. PrC | Page 11 of 13
AD8366 PARALLEL AND SERIAL INTERFACE TIMING
1 CS 0 1 SCLK 0
Preliminary Technical Data
t0 t1 t2 t3 t4
1 SDATA 0
B-LSB LOAD DATA INTO SERIAL REGISTER ON RISING EDGE.
B-MSB
A-LSB
A-MSB
TRANSFER DATA FROM SERIAL REGISTER TO PARALLEL LATCHES ON LE FALLING EDGE.
1 SENB 0
Figure 11. SPI Port Timing Diagram
1 BIT[0-6] 0 1 DENA 0 X GAIN A X GAIN B X GAIN A/B X
t1 t2
t0
1 DENB 0
t3
1 SENB 0 PROGRAM A ONLY PROGRAM B ONLY PROGRAM A AND B
Figure 12. Parallel Port Timing Diagram
Rev. PrC | Page 12 of 13
Preliminary Technical Data OUTLINE DIMENSIONS
32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 x 5 mm Body, Very Thin Quad (CP-32-4) Dimensions shown in millimeters
AD8366
5.00 BSC SQ
0.60 MAX 0.60 MAX
25 24 32 1
PIN 1 INDICATOR
PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ
0.50 BSC
EXPOSED PAD (BOTTOM VIEW)
3.65 3.50 SQ 3.35
8
0.50 0.40 0.30
12 MAX
17 16
9
0.25 MIN 3.50 REF
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
1.00 0.85 0.80
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 13. Outline Dimensions.
ORDERING GUIDE
Model AD8366-EVALZ Temperature Range Package Description Evaluation Board Package Option
Rev. PrC | Page 13 of 13
PR07584-0-6/08(PrC)

▲Up To Search▲

Price & Availability of AD8366

	To Download AD8366 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .